1. Field of the Invention
This invention relates to the field of data processing systems and, in particular, to the field of arbitration of requests for access to a common memory in data processing systems.
2. Background Art
It is well known in the art to provide data processing systems wherein a number of data processing devices require access to a common memory. Additionally, it is known in the field of video image processing, which requires both encoded image data and decoded image data, to provide memories for storing both kinds of data for each of these various devices. In order to reduce the costs of such an image processing system it may be desirable to use a single memory to hold both the encoded image data and decoded image data of the various devices.
A memory of this type may be adapted for access by a source of compressed video data in order for the compressed data source to store the encoded data; for access by a decoding data processor in order to read the encoded data, decode it, store it; and also for access by a display processor in order to read the decoded data and display it. Since each of these devices accesses the common memory for a number of different purposes, there is a high likelihood of a conflict between them whenever the common memory is accessed for two different purposes at the same time.
One method for resolving conflicting memory access requests by the various devices is to use a fixed priority scheme in which each type of memory access from each device is assigned a fixed priority. In this method the type of pending request having the highest priority is processed first. A system of this type is disclosed in U.S. Pat. No. 4,564,915, entitled "YIQ Computer Graphics System", which is hereby incorporated by reference.
However, a fixed priority memory arbitration system may have disadvantages in some video signal processing system applications. For example, in the system described above the memory read request from the data decoding processor may have a higher priority than the memory write request from the data decoding processor. Under these conditions, when the output buffer of the decoding processor is full and a memory read operation is requested, the processor must wait until both the read and write operations have been processed before new data may be added to the output buffer.
If, however, the memory write operation has a higher priority than the memory read operation, the processor would only wait for the memory write operation. It can process data previously stored in an input buffer while the memory read operation is in progress. Any unnecessary delay in the operation of a video signal processor may preclude that processor from decoding the encoded data for an image quickly enough to produce a display with natural detail and motion. It may be desirable, therefore, for a video signal processor to have a flexible system for the arbitration of memory access conflicts which avoids unnecessary delay in the operation of the processor in some applications.
A more flexible arbitration scheme is disclosed in U.S. Pat. No. 5,088,053. U.S. Pat. No. 5,088,053 teaches a memory control system for a video signal processor which includes an input channel for reading data from a memory and an output channel for writing data into a memory. The memory control system includes circuitry coupled to the input channel and circuity coupled to the output channel for requesting both a memory operation with a normal priority and for requesting a memory operation with an urgent priority. A scheduling circuit for normal requests receives the normal priority requests provided by the input and output channel and schedules normal memory operations to satisfy these requests with substantially equal priority. Another scheduling circuit, an urgent scheduling circuit, receives the urgent requests from the input and output channels. When an urgent request is received, the urgent scheduling circuit disables the normal scheduling circuit and schedules memory operations according to a different priority scheme. However, this system does not permit easy access for high priority devices while guaranteeing that low priority devices are not locked out.